Efficient Bit-Level Model Reductions for Automated Hardware Verification

Sergey Tverdyshev, Eyad Alkassar. Efficient Bit-Level Model Reductions for Automated Hardware Verification. In Stéphane Demri, Christian S. Jensen, editors, 15th International Symposium on Temporal Representation and Reasoning, TIME 2008, Université du Québec à Monteéal, Canada, 16-18 June 2008. pages 164-172, IEEE Computer Society, 2008. [doi]

@inproceedings{TverdyshevA08,
  title = {Efficient Bit-Level Model Reductions for Automated Hardware Verification},
  author = {Sergey Tverdyshev and Eyad Alkassar},
  year = {2008},
  doi = {10.1109/TIME.2008.11},
  url = {http://dx.doi.org/10.1109/TIME.2008.11},
  researchr = {https://researchr.org/publication/TverdyshevA08},
  cites = {0},
  citedby = {0},
  pages = {164-172},
  booktitle = {15th International Symposium on Temporal Representation and Reasoning, TIME 2008, Université du Québec à Monteéal, Canada, 16-18 June 2008},
  editor = {Stéphane Demri and Christian S. Jensen},
  publisher = {IEEE Computer Society},
  isbn = {978-0-7695-3181-6},
}