A 90 nm FPGA I/O buffer design with 1.6 Gbps data rate for source-synchronous system and 300 MHz clock rate for external memory interface - researchr publication bibliographies

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Jeffrey Tyhach, Bonnie Wang, Chiakang Sung, Joseph Huang, Khai Nguyen, Xiaobao Wang, Yan Chong, Phlip Pan, Henry Kim, Gopinath Rangan, Tzung-Chin Chang, Johnson Tan. A 90 nm FPGA I/O buffer design with 1.6 Gbps data rate for source-synchronous system and 300 MHz clock rate for external memory interface. In Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC 2004, Orlando, FL, USA, October 2004. pages 431-434, IEEE, 2004. [doi]

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