A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block - researchr publication related

researchr

You are not signed in
Sign in
Sign up

Chetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas. A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block. In International Symposium on Electronic System Design, ISED 2011, Kochi, Kerala, India, December 19-21, 2011. pages 100-105, IEEE, 2011. [doi]

The following publications are possibly variants of this publication:

Increment/decrement/2's complement/priority encoder circuit for varying operand lengthsSai Phaneendra P., Chetan Vudadha, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas. iscit 2011: 472-477 [doi]

runs on WebDSL