The relationship between border traps characterized by AC admittance and BTI in III-V MOS devices

Abhitosh Vais, Koen Martens, J. Franco, D. Lin, A. Alian, Philippe Roussel, S. Sioncke, Nadine Collaert, Aaron Thean, Marc M. Heyns, Guido Groeseneken, Kristin De Meyer. The relationship between border traps characterized by AC admittance and BTI in III-V MOS devices. In IEEE International Reliability Physics Symposium, IRPS 2015, Monterey, CA, USA, April 19-23, 2015. pages 5, IEEE, 2015. [doi]

@inproceedings{VaisMFLARSCTHGD15,
  title = {The relationship between border traps characterized by AC admittance and BTI in III-V MOS devices},
  author = {Abhitosh Vais and Koen Martens and J. Franco and D. Lin and A. Alian and Philippe Roussel and S. Sioncke and Nadine Collaert and Aaron Thean and Marc M. Heyns and Guido Groeseneken and Kristin De Meyer},
  year = {2015},
  doi = {10.1109/IRPS.2015.7112742},
  url = {http://dx.doi.org/10.1109/IRPS.2015.7112742},
  researchr = {https://researchr.org/publication/VaisMFLARSCTHGD15},
  cites = {0},
  citedby = {0},
  pages = {5},
  booktitle = {IEEE International Reliability Physics Symposium, IRPS 2015, Monterey, CA, USA, April 19-23, 2015},
  publisher = {IEEE},
  isbn = {978-1-4673-7362-3},
}