An Information Theoretical Framework for Analysis and Design of Nanoscale Fault-Tolerant Memories Based on Low-Density Parity-Check Codes

Bane V. Vasic, Shashi Kiran Chilappagari. An Information Theoretical Framework for Analysis and Design of Nanoscale Fault-Tolerant Memories Based on Low-Density Parity-Check Codes. IEEE Trans. on Circuits and Systems, 54-I(11):2438-2446, 2007. [doi]

@article{VasicC07,
  title = {An Information Theoretical Framework for Analysis and Design of Nanoscale Fault-Tolerant Memories Based on Low-Density Parity-Check Codes},
  author = {Bane V. Vasic and Shashi Kiran Chilappagari},
  year = {2007},
  doi = {10.1109/TCSI.2007.902611},
  url = {http://dx.doi.org/10.1109/TCSI.2007.902611},
  researchr = {https://researchr.org/publication/VasicC07},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. on Circuits and Systems},
  volume = {54-I},
  number = {11},
  pages = {2438-2446},
}