Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits - researchr publication

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V. Vasudevan. Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits. In William H. Joyner Jr., Grant Martin, Andrew B. Kahng, editors, Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005. pages 397-402, ACM, 2005. [doi]

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