A Family of Area-Time Efficient Modulo 2n+1 Adders

Haridimos T. Vergos. A Family of Area-Time Efficient Modulo 2n+1 Adders. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2010, 5-7 July 2010, Lixouri Kefalonia, Greece. pages 442-443, IEEE Computer Society, 2010. [doi]

Abstract

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