Haridimos T. Vergos, Dimitris Bakalis. On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components. In Luca Fanucci, editor, 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008. pages 752-759, IEEE, 2008. [doi]
Abstract is missing.