A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy

Naveen Verma, Anantha P. Chandrakasan. A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy. In 2007 IEEE International Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, San Francisco, CA, USA, February 11-15, 2007. pages 328-606, IEEE, 2007. [doi]

Abstract

Abstract is missing.