7.5 Gb/s monolithically integrated clock recovery circuit using PLL and 0.3-/spl mu/m gate length quantum well HEMT's

Zhi-Gong Wang, Manfred Berroth, Ulrich Nowotny, Peter Hofmann, Axel Hiilsmann, Klaus Köhler, Brian Raynor, Joachim Schneider. 7.5 Gb/s monolithically integrated clock recovery circuit using PLL and 0.3-/spl mu/m gate length quantum well HEMT's. J. Solid-State Circuits, 29(8):995-997, August 1994. [doi]

Abstract

Abstract is missing.