A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop

Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen. A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop. VLSI Design, 2000(2):107-113, 2000. [doi]

Abstract

Abstract is missing.