Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package - researchr publication authors

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Kai-li Wang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang. Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package. IEEE Design & Test of Computers, 34(3):50-58, 2017. [doi]

This author has not been identified. Look up 'Kai-li Wang' in GoogleThis author has not been identified. Look up 'Bing-Yang Lin' in GoogleThis author has not been identified. Look up 'Cheng-Wen Wu' in GoogleThis author has not been identified. Look up 'Mincent Lee' in GoogleThis author has not been identified. It may be one of the following persons:

Hao Chen

Look up 'Hao Chen' in GoogleThis author has not been identified. Look up 'Hung-Chih Lin' in GoogleThis author has not been identified. Look up 'Ching-Nen Peng' in GoogleThis author has not been identified. Look up 'Min-Jer Wang' in Google

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