Kai-li Wang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang. Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package. IEEE Design & Test of Computers, 34(3):50-58, 2017. [doi]
@article{WangLWLCLPW17,
title = {Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package},
author = {Kai-li Wang and Bing-Yang Lin and Cheng-Wen Wu and Mincent Lee and Hao Chen and Hung-Chih Lin and Ching-Nen Peng and Min-Jer Wang},
year = {2017},
doi = {10.1109/MDAT.2016.2562060},
url = {https://doi.org/10.1109/MDAT.2016.2562060},
researchr = {https://researchr.org/publication/WangLWLCLPW17},
cites = {0},
citedby = {0},
journal = {IEEE Design & Test of Computers},
volume = {34},
number = {3},
pages = {50-58},
}