A gate sizing method for glitch power reduction

Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz. A gate sizing method for glitch power reduction. In IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, September 26-28, 2011. pages 24-29, IEEE, 2011. [doi]

Abstract

Abstract is missing.