Power gating topologies in TSV based 3D integrated circuits

Hailang Wang, Emre Salman. Power gating topologies in TSV based 3D integrated circuits. In José Luis Ayala, Alex K. Jones, Patrick H. Madden, Ayse Kivilcim Coskun, editors, Great Lakes Symposium on VLSI 2013 (part of ECRC), GLSVLSI'13, Paris, France, May 2-4, 2013. pages 327-328, ACM, 2013. [doi]

Abstract

Abstract is missing.