Power gating topologies in TSV based 3D integrated circuits - researchr publication related

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Hailang Wang, Emre Salman. Power gating topologies in TSV based 3D integrated circuits. In José Luis Ayala, Alex K. Jones, Patrick H. Madden, Ayse Kivilcim Coskun, editors, Great Lakes Symposium on VLSI 2013 (part of ECRC), GLSVLSI'13, Paris, France, May 2-4, 2013. pages 327-328, ACM, 2013. [doi]

The following publications are possibly variants of this publication:

Decoupling Capacitor Topologies for TSV-Based 3-D ICs With Power GatingHailang Wang, Emre Salman. tvlsi, 23(12):2983-2991, 2015. [doi]

TSVs-aware floorplanning for 3D integrated circuitJieliang Lu, Qin Wang, Jing Xie, Zhigang Mao. asicon 2013: 1-4 [doi]

Thermal management of coaxial through-silicon-via (C-TSV)-based three-dimensional integrated circuit (3D IC)Fengjuan Wang, Ningmei Yu. ieiceee, 13(11):20151117, 2016. [doi]

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