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An 80MHz-BW 31.9fJ/conv-step Filtering ΔΣ ADC with a Built-In DAC-Segmentation/ELD-Compensation 6b 960MS/s SAR-Quantizer in 28nm LP for 802.11ax Applications

Chi-Yun Wang, Jen-Huan Tsai, Sheng-Yuan Su, Jen-Che Tsai, Jhy-Rong Chen, Chih-Hong Lou. An 80MHz-BW 31.9fJ/conv-step Filtering ΔΣ ADC with a Built-In DAC-Segmentation/ELD-Compensation 6b 960MS/s SAR-Quantizer in 28nm LP for 802.11ax Applications. In IEEE International Solid- State Circuits Conference, ISSCC 2019, San Francisco, CA, USA, February 17-21, 2019. pages 338-340, IEEE, 2019. [doi]

Authors

Chi-Yun Wang

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Jen-Huan Tsai

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Sheng-Yuan Su

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Jen-Che Tsai

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Jhy-Rong Chen

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Chih-Hong Lou

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