Chi-Yun Wang, Jen-Huan Tsai, Sheng-Yuan Su, Jen-Che Tsai, Jhy-Rong Chen, Chih-Hong Lou. An 80MHz-BW 31.9fJ/conv-step Filtering ΔΣ ADC with a Built-In DAC-Segmentation/ELD-Compensation 6b 960MS/s SAR-Quantizer in 28nm LP for 802.11ax Applications. In IEEE International Solid- State Circuits Conference, ISSCC 2019, San Francisco, CA, USA, February 17-21, 2019. pages 338-340, IEEE, 2019. [doi]
@inproceedings{WangTSTCL19,
title = {An 80MHz-BW 31.9fJ/conv-step Filtering ΔΣ ADC with a Built-In DAC-Segmentation/ELD-Compensation 6b 960MS/s SAR-Quantizer in 28nm LP for 802.11ax Applications},
author = {Chi-Yun Wang and Jen-Huan Tsai and Sheng-Yuan Su and Jen-Che Tsai and Jhy-Rong Chen and Chih-Hong Lou},
year = {2019},
doi = {10.1109/ISSCC.2019.8662416},
url = {https://doi.org/10.1109/ISSCC.2019.8662416},
researchr = {https://researchr.org/publication/WangTSTCL19},
cites = {0},
citedby = {0},
pages = {338-340},
booktitle = {IEEE International Solid- State Circuits Conference, ISSCC 2019, San Francisco, CA, USA, February 17-21, 2019},
publisher = {IEEE},
isbn = {978-1-5386-8531-0},
}