Takao Watanabe, Ryo Fujita, Kazumasa Yanagisawa, Hitoshi Tanaka, Kazushige Ayukawa, Mitsuru Soga, Yuji Tanaka, Yoshimitsu Sugie, Yoshinobu Nakagome. A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integrated media chip. J. Solid-State Circuits, 32(5):635-641, 1997. [doi]
Abstract is missing.