A fully automated verilog-to-layout synthesized ADC demonstrating 56dB-SNDR with 2MHz-BW - researchr publication

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Allen Waters, Un-Ku Moon. A fully automated verilog-to-layout synthesized ADC demonstrating 56dB-SNDR with 2MHz-BW. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2015, Xia'men, China, November 9-11, 2015. pages 1-4, IEEE, 2015. [doi]

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