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I-Chyn Wey, Chun-Wei Chang, Yu-Cheng Liao, Heng-Jui Chou. Noise-tolerant dynamic CMOS circuits design by using true single-phase clock latching technique. I. J. Circuit Theory and Applications, 43(7):854-865, 2015. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS CircuitsI-Chyn Wey, You-Gang Chen, An-Yeu Wu. tvlsi, 16(12):1708-1712, 2008. [doi]
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