Daniel Weyer, Mehmet Batuhan Dayanik, Sunmin Jang, Michael P. Flynn. 2 40nm CMOS fractional-N FMCW chirp synthesizer PLL with a continuous-time bandpass delta-sigma time-to-digital converter. In 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018. pages 250-252, IEEE, 2018. [doi]
Abstract is missing.