Performance evaluation for system-on-chip architectures using trace-based transaction level simulation

Thomas Wild, Andreas Herkersdorf, Rainer Ohlendorf. Performance evaluation for system-on-chip architectures using trace-based transaction level simulation. In Georges G. E. Gielen, editor, Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006. pages 248-253, European Design and Automation Association, Leuven, Belgium, 2006. [doi]

Abstract

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