Performance evaluation for system-on-chip architectures using trace-based transaction level simulation

Thomas Wild, Andreas Herkersdorf, Rainer Ohlendorf. Performance evaluation for system-on-chip architectures using trace-based transaction level simulation. In Georges G. E. Gielen, editor, Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006. pages 248-253, European Design and Automation Association, Leuven, Belgium, 2006. [doi]

@inproceedings{WildHO06,
  title = {Performance evaluation for system-on-chip architectures using trace-based transaction level simulation},
  author = {Thomas Wild and Andreas Herkersdorf and Rainer Ohlendorf},
  year = {2006},
  doi = {10.1145/1131549},
  url = {http://doi.acm.org/10.1145/1131549},
  tags = {architecture},
  researchr = {https://researchr.org/publication/WildHO06},
  cites = {0},
  citedby = {0},
  pages = {248-253},
  booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany,  March 6-10, 2006},
  editor = {Georges G. E. Gielen},
  publisher = {European Design and Automation Association, Leuven, Belgium},
  isbn = {3-9810801-0-6},
}