Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler. Reversible Logic Synthesis with Output Permutation. In VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009. pages 189-194, IEEE, 2009. [doi]
Abstract is missing.