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Designing a RISC CPU in Reversible Logic

Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler. Designing a RISC CPU in Reversible Logic. In Frank Oppenheimer, editor, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Oldenburg, Germany, February 21-23, 2011. pages 249-258, OFFIS-Institut für Informatik, 2011.

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