A 160 ns 54 bit CMOS division implementation using self-timing and symmetrically overlapped SRT stages - researchr publication

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Ted E. Williams, Mark A. Horowitz. A 160 ns 54 bit CMOS division implementation using self-timing and symmetrically overlapped SRT stages. In 10th IEEE Symposium on Computer Arithmetic, ARITH 1991, Grenoble, France, June 26-28, 1991. pages 210-217, IEEE, 1991. [doi]

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