Automated transistor sizing algorithm for minimizing spurious switching activities in CMOS circuits

A. Wroblewski, C. V. Schimpfle, J. A. Nossek. Automated transistor sizing algorithm for minimizing spurious switching activities in CMOS circuits. In IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings. pages 291-294, IEEE, 2000. [doi]

Abstract

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