A Multiple-Stage Parallel Replica-Bitline Delay Addition Technique for Reducing Timing Variation of SRAM Sense Amplifiers - researchr publication

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Jianhui Wu, Jiafeng Zhu, YingCheng Xia, Na Bai. A Multiple-Stage Parallel Replica-Bitline Delay Addition Technique for Reducing Timing Variation of SRAM Sense Amplifiers. IEEE Trans. on Circuits and Systems, 61-II(4):264-268, 2014. [doi]

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