A 0.5V-to-0.9V 0.2GHz-to-5GHz Ultra-Low-Power Digitally-Assisted Analog Ring PLL with Less Than 200ns Lock Time in 22nm FinFET CMOS Technology

Bo Xiang, Yongping Fan, James S. Ayers, James Shen, Dan Zhang. A 0.5V-to-0.9V 0.2GHz-to-5GHz Ultra-Low-Power Digitally-Assisted Analog Ring PLL with Less Than 200ns Lock Time in 22nm FinFET CMOS Technology. In 2020 IEEE Custom Integrated Circuits Conference, CICC 2020, Boston, MA, USA, March 22-25, 2020. pages 1-4, IEEE, 2020. [doi]

@inproceedings{XiangFASZ20,
  title = {A 0.5V-to-0.9V 0.2GHz-to-5GHz Ultra-Low-Power Digitally-Assisted Analog Ring PLL with Less Than 200ns Lock Time in 22nm FinFET CMOS Technology},
  author = {Bo Xiang and Yongping Fan and James S. Ayers and James Shen and Dan Zhang},
  year = {2020},
  doi = {10.1109/CICC48029.2020.9075897},
  url = {https://doi.org/10.1109/CICC48029.2020.9075897},
  researchr = {https://researchr.org/publication/XiangFASZ20},
  cites = {0},
  citedby = {0},
  pages = {1-4},
  booktitle = {2020 IEEE Custom Integrated Circuits Conference, CICC 2020, Boston, MA, USA, March 22-25, 2020},
  publisher = {IEEE},
  isbn = {978-1-7281-6031-3},
}