An experimental soft-error-immune 64-kbit 3-ns ECL bipolar RAM

Kunihiko Yamaguchi, Hiroaki Nanbu, Kazuo Kanetani, Noriyuki Homma, Tohru Nakamura, Kenichi Ohhata, Akihisa Uchida, Katsumi Ogiue. An experimental soft-error-immune 64-kbit 3-ns ECL bipolar RAM. J. Solid-State Circuits, 24(5):1390-1396, October 1989. [doi]

@article{YamaguchiNKHNOUO89,
  title = {An experimental soft-error-immune 64-kbit 3-ns ECL bipolar RAM},
  author = {Kunihiko Yamaguchi and Hiroaki Nanbu and Kazuo Kanetani and Noriyuki Homma and Tohru Nakamura and Kenichi Ohhata and Akihisa Uchida and Katsumi Ogiue},
  year = {1989},
  month = {October},
  doi = {10.1109/JSSC.1989.572620},
  url = {https://doi.org/10.1109/JSSC.1989.572620},
  researchr = {https://researchr.org/publication/YamaguchiNKHNOUO89},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {24},
  number = {5},
  pages = {1390-1396},
}