PD Constraint-aware Physical/Logical Topology Co-Design for Network on Wafer

Qize Yang, Taiquan Wei, Sihan Guan, Chengran Li, Haoran Shang, Jinyi Deng, Huizheng Wang, Chao Li, Lei Wang, Yan Zhang, Shouyi Yin, Yang Hu. PD Constraint-aware Physical/Logical Topology Co-Design for Network on Wafer. In Proceedings of the 52nd Annual International Symposium on Computer Architecture, ISCA 2025, Tokyo, Japan, June 21-25, 2025. pages 49-64, ACM, 2025. [doi]

Abstract

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