A scalable hardware architecture for multi-layer spiking neural networks

Zhaozhong Ying, Chong Luo, Xiaolei Zhu. A scalable hardware architecture for multi-layer spiking neural networks. In Yajie Qin, Zhiliang Hong, Ting-Ao Tang, editors, 12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017. pages 839-842, IEEE, 2017. [doi]

Abstract

Abstract is missing.