A CMOS 5.4/3.24Gbps dual-rate clock and data recovery design for DisplayPort v1.2

Jae Wook Yoo, Tae-Ho Kim, Dong-Kyun Kim, Jin-Ku Kang. A CMOS 5.4/3.24Gbps dual-rate clock and data recovery design for DisplayPort v1.2. In Thomas B├╝chner, Ramalingam Sridhar, Andrew Marshall, Norbert Schuhmann, editors, Annual IEEE International SoC Conference, SoCC 2010, September 27-29, 2010, Las Vegas, NV, USA, Proceedings. pages 88-91, IEEE, 2010. [doi]

Abstract

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