Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout

Shusuke Yoshimoto, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto. Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout. IEICE Transactions, 96-A(7):1579-1585, 2013. [doi]

Abstract

Abstract is missing.