A 6.5-12.5-Gb/s Half-Rate Single-Loop All-Digital Referenceless CDR in 28-nm CMOS

Changzhi Yu, Euije Sa, Soowan Jin, Himchan Park, Jongshin Shin, Jinwook Burm. A 6.5-12.5-Gb/s Half-Rate Single-Loop All-Digital Referenceless CDR in 28-nm CMOS. J. Solid-State Circuits, 55(10):2831-2841, 2020. [doi]

Authors

Changzhi Yu

This author has not been identified. Look up 'Changzhi Yu' in Google

Euije Sa

This author has not been identified. Look up 'Euije Sa' in Google

Soowan Jin

This author has not been identified. Look up 'Soowan Jin' in Google

Himchan Park

This author has not been identified. Look up 'Himchan Park' in Google

Jongshin Shin

This author has not been identified. Look up 'Jongshin Shin' in Google

Jinwook Burm

This author has not been identified. Look up 'Jinwook Burm' in Google