A 6.5-12.5-Gb/s Half-Rate Single-Loop All-Digital Referenceless CDR in 28-nm CMOS

Changzhi Yu, Euije Sa, Soowan Jin, Himchan Park, Jongshin Shin, Jinwook Burm. A 6.5-12.5-Gb/s Half-Rate Single-Loop All-Digital Referenceless CDR in 28-nm CMOS. J. Solid-State Circuits, 55(10):2831-2841, 2020. [doi]

@article{YuSJPSB20,
  title = {A 6.5-12.5-Gb/s Half-Rate Single-Loop All-Digital Referenceless CDR in 28-nm CMOS},
  author = {Changzhi Yu and Euije Sa and Soowan Jin and Himchan Park and Jongshin Shin and Jinwook Burm},
  year = {2020},
  doi = {10.1109/JSSC.2020.3005750},
  url = {https://doi.org/10.1109/JSSC.2020.3005750},
  researchr = {https://researchr.org/publication/YuSJPSB20},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {55},
  number = {10},
  pages = {2831-2841},
}