Sharareh Zamanzadeh, Ali Jahanian. Automatic netlist scrambling methodology in ASIC design flow to hinder the reverse engineering. In Martin Margala, Ricardo Augusto da Luz Reis, Alex Orailoglu, Luigi Carro, Luis Miguel Silveira, H. Fatih Ugurdag, editors, 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013. pages 52-53, IEEE, 2013. [doi]
Abstract is missing.