Feng Zhang 0014, Hao Ju, Chengying Chen. A PVT variation tolerant and low power 5Gb/s clock and data recovery circuit for PCI-E 2.0/USB 3.0. In 2015 IEEE 11th International Conference on ASIC, ASICON 2015, Chengdu, China, November 3-6, 2015. pages 1-4, IEEE, 2015. [doi]
Abstract is missing.