A low active and leakage power SRAM using a read and write divided and BIST programmable timing control circuit

Jiafeng Zhu, Na Bai, Jianhui Wu. A low active and leakage power SRAM using a read and write divided and BIST programmable timing control circuit. Microelectronics Journal, 44(4):283-291, 2013. [doi]

Abstract

Abstract is missing.