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Junheng Zhu, Woo-seok Choi, Pavan Kumar Hanumolu. 2 0.26- $\mu$ W/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS. J. Solid-State Circuits, 54(8):2186-2194, 2019. [doi]
Abstract is missing.