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Low-power test planning for arbitrary at-speed delay-test clock schemes

Christian G. Zoellin, Hans-Joachim Wunderlich. Low-power test planning for arbitrary at-speed delay-test clock schemes. In 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA. pages 93-98, IEEE Computer Society, 2010. [doi]

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