Abstract is missing.
- Biologically-Inspired Massively-Parallel Architectures - Computing Beyond a Million ProcessorsStephen B. Furber, Andrew D. Brown. 3-12 [doi]
- Formal Verification of Lock-Free AlgorithmsGerhard Schellhorn, Simon Bäumler. 13-18 [doi]
- Examining Important Corner Cases: Verification of Interacting Architectural Components in System DesignsYosinori Watanabe. 19 [doi]
- Teak: A Token-Flow Implementation for the Balsa LanguageAndrew Bardsley, Luis A. Tarazona, Doug A. Edwards. 23-31 [doi]
- Desynchronizing Synchronous Programs by ModesJens Brandt, Mike Gemunde, Klaus Schneider. 32-41 [doi]
- From Concurrent Multi-clock Programs to Deterministic Asynchronous ImplementationsDumitru Potop-Butucaru, Robert de Simone, Yves Sorel, Jean-Pierre Talpin. 42-51 [doi]
- Scheduling Synchronous Elastic DesignsJosep Carmona, Jorge Júlvez, Jordi Cortadella, Michael Kishinevsky. 52-59 [doi]
- Saving Space in a Time Efficient Simulation AlgorithmSilvia Crafa, Francesco Ranzato, Francesco Tapparo. 60-69 [doi]
- Checking pi-Calculus Structural Congruence is Graph Isomorphism CompleteVictor Khomenko, Roland Meyer. 70-79 [doi]
- Petrifying Operating Guidelines for ServicesNiels Lohmann, Karsten Wolf. 80-88 [doi]
- Variants of the Language Based Synthesis Problem for Petri NetsSebastian Mauser, Robert Lorenz. 89-98 [doi]
- Flat ArbitersAndrey Mokhov, Victor Khomenko, Alexandre Yakovlev. 99-108 [doi]
- Trading Off Concurrency to Generate Behavioral AdaptersArjan J. Mooij, Marc Voorhoeve. 109-118 [doi]
- Why Are Modalities Good for Interface Theories?Jean-Baptiste Raclet, Eric Badouel, Albert Benveniste, Benoît Caillaud, Roberto Passerone. 119-127 [doi]
- Model Checking Verilog Descriptions of Cell LibrariesMatthias Raffelsieper, Jan-Willem Roorda, Mohammad Reza Mousavi. 128-137 [doi]
- Time Arc Petri Nets and Their AnalysisHind Rakkay, Hanifa Boucheneb, Olivier H. Roux. 138-147 [doi]
- Specification Enforcing Refinement for Convertibility VerificationPartha S. Roop, Alain Girault, Roopak Sinha, Gregor Goessler. 148-157 [doi]
- Parameterised Process Algebraic Verification by Precongruence ReductionAntti Siirtola, Juha Kortelainen. 158-167 [doi]
- Verifying Deadlock- and Livelock Freedom in an SOA ScenarioKarsten Wolf, Christian Stahl, Janine Ott, Robert Danitz. 168-177 [doi]
- Genet: A Tool for the Synthesis and Mining of Petri NetsJosep Carmona, Jordi Cortadella, Michael Kishinevsky. 181-185 [doi]
- DESIJ--Enabling Decomposition-Based Synthesis of Complex Asynchronous ControllersMark Schäfer, Dominic Wist, Ralf Wollowski. 186-190 [doi]