Abstract is missing.
- High-Performance Energy-Efficient Reconfigurable Accelerators/Co-processors for Tera-Scale Multi-core MicroprocessorsRam Krishnamurthy. 1 [doi]
- Process Variability and Degradation: New Frontier for ReconfigurablePeter Y. K. Cheung. 2 [doi]
- Towards Analytical Methods for FPGA Architecture InvestigationSteven J. E. Wilton. 3 [doi]
- Generic Systolic Array for Run-Time Scalable CoresAndrés Otero, Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo. 4-16 [doi]
- Virtualization within a Parallel Array of Homogeneous Processing UnitsMarc Stöttinger, Alexander Biedermann, Sorin Alexander Huss. 17-28 [doi]
- Feasibility Study of a Self-healing Hardware PlatformMichael Reibel Boesen, Pascal Schleuniger, Jan Madsen. 29-41 [doi]
- Application-Specific Signatures for Transactional Memory in Soft ProcessorsMartin Labrecque, Mark Jeffrey, J. Gregory Steffan. 42-54 [doi]
- Towards Rapid Dynamic Partial Reconfiguration in Video-Based Driver Assistance SystemsChristopher Claus, Rehan Ahmed, Florian Altenried, Walter Stechele. 55-67 [doi]
- Parametric Encryption Hardware DesignAdrien Le Masle, Wayne Luk, Jared Eldredge, Kris Carver. 68-79 [doi]
- A Reconfigurable Implementation of the Tate Pairing Computation over ::::GF::::(2:::::::m:::::::)Weibo Pan, William P. Marnane. 80-91 [doi]
- Application Specific FPGA Using Heterogeneous Logic BlocksHusain Parvez, Zied Marrakchi, Habib Mehrez. 92-109 [doi]
- Reconfigurable Communication Networks in a Parametric SIMD Parallel System on ChipMouna Baklouti, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid. 110-121 [doi]
- A Dedicated Reconfigurable Architecture for Finite State MachinesJohann Glaser, Markus Damm, Jan Haase, Christoph Grimm. 122-133 [doi]
- MEMS Dynamic Optically Reconfigurable Gate Array Usable under a Space Radiation EnvironmentDaisaku Seto, Minoru Watanabe. 134-144 [doi]
- An FPGA Accelerator for Hash Tree Generation in the Merkle Signature SchemeAbdulhadi Shoufan. 145-156 [doi]
- A Fused Hybrid Floating-Point and Fixed-Point Dot-Product for FPGAsAntonio Roldao Lopes, George A. Constantinides. 157-168 [doi]
- Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative MethodsDavid Boland, George A. Constantinides. 169-181 [doi]
- Design of a Financial Application Driven Multivariate Gaussian Random Number Generator for an FPGAChalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides. 182-193 [doi]
- 3D Compaction: A Novel Blocking-Aware Algorithm for Online Hardware Task Scheduling and Placement on 2D Partially Reconfigurable DevicesThomas Marconi, Yi Lu 0004, Koen Bertels, Georgi Gaydadjiev. 194-206 [doi]
- TROUTE: A Reconfigurability-Aware FPGA RouterKarel Bruneel, Dirk Stroobandt. 207-218 [doi]
- Space and Time Sharing of Reconfigurable Hardware for Accelerated Parallel ProcessingEsam El-Araby, Vikram K. Narayana, Tarek A. El-Ghazawi. 219-230 [doi]
- Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable ArchitectureGanghee Lee, Seokhyun Lee, Kiyoung Choi, Nikil D. Dutt. 231-243 [doi]
- Design Automation for Reconfigurable Interconnection NetworksHongbing Fan, Yu-Liang Wu, Chak-Chung Cheung. 244-256 [doi]
- A Framework for Enabling Fault Tolerance in Reconfigurable ArchitecturesKostas Siozios, Dimitrios Soudris, Dionisios N. Pnevmatikatos. 257-268 [doi]
- QUAD - A Memory Access Pattern AnalyserS. Arash Ostadzadeh, Roel Meeuws, Carlo Galuzzi, Koen Bertels. 269-281 [doi]
- Hierarchical Loop Partitioning for Rapid Generation of Runtime ConfigurationsSiew Kei Lam, Yun Deng, Jian Hu, Xilong Zhou, Thambipillai Srikanthan. 282-293 [doi]
- Reconfigurable Computing and Task Scheduling for Active Storage Service ProcessingYu Zhang, Dan Feng. 294-305 [doi]
- A Reconfigurable Disparity Engine for Stereovision in Advanced Driver Assistance SystemsMehdi Darouich, Stéphane Guyetant, Dominique Lavenier. 306-317 [doi]
- A Modified Merging Approach for Datapath Configuration Time ReductionMahmood Fazlali, Ali Zakerolhosseini, Georgi Gaydadjiev. 318-328 [doi]
- Reconfigurable Computing Education in Computer ScienceAbdulhadi Shoufan, Sorin Alexander Huss. 329-336 [doi]
- Hardware Implementation of the Orbital Function for Quantum Chemistry CalculationsMaciej Wielgosz, Ernest Jamro, Pawel Russek, Kazimierz Wiatr. 337-342 [doi]
- Reconfigurable Polyphase Filter Bank Architecture for Spectrum SensingSuhaib A. Fahmy, Linda Doyle. 343-350 [doi]
- Systolic Algorithm Mapping for Coarse Grained Reconfigurable Array ArchitecturesKunjan Patel, Chris J. Bleakley. 351-357 [doi]
- A GMM-Based Speaker Identification System on FPGAPhak Len Eh Kan, Tim Allen, Steven F. Quigley. 358-363 [doi]
- An FPGA-Based Real-Time Event SamplerNiels Penneman, Luc Perneel, Martin Timmerman, Bjorn De Sutter. 364-371 [doi]
- A Performance Evaluation of CUBE: One-Dimensional 512 FPGA ClusterMasato Yoshimi, Yuri Nishikawa, Mitsunori Miki, Tomoyuki Hiroyasu, Hideharu Amano, Oskar Mencer. 372-381 [doi]
- An Analysis of Delay Based PUF Implementations on FPGASergey Morozov, Abhranil Maiti, Patrick Schaumont. 382-387 [doi]
- Comparison of Bit Serial Computation with Bit Parallel Computation for Reconfigurable ProcessorKazuya Tanigawa, Ken ichi Umeda, Tetsuo Hironaka. 388-393 [doi]
- FPGA Implementation of QR Decomposition Using MGS AlgorithmAkkarat Boonpoonga, Sompop Janyavilas, Phaophak Sirisuk, Monai Krairiksh. 394-399 [doi]
- Memory-Centric Communication Architecture for Reconfigurable ComputingKyungwook Chang, Kiyoung Choi. 400-405 [doi]
- Integrated Design Environment for Reconfigurable HPCLilian Janin, Shoujie Li, Doug Edwards. 406-413 [doi]
- Architecture-Aware Custom Instruction Generation for Reconfigurable ProcessorsAlok Prakash, Siew Kei Lam, Amit Kumar Singh, Thambipillai Srikanthan. 414-419 [doi]
- Cost and Performance Evaluation of a Noise Filter for Partitioning in Co-design MethodologiesVictoria Rodellar, Elvira MartÃnez de Icaya, Francisco DÃaz, Virginia Peinado. 420-425 [doi]
- Towards a Tighter Integration of Generated and Custom-Made HardwareHarald Devos, Wim Meeus, Dirk Stroobandt. 426-434 [doi]
- Pipelined Microprocessors Optimization and DebuggingBijan Alizadeh, Amir Masoud Gharehbaghi, Masahiro Fujita. 435-444 [doi]