Table of Contents

• Hybrid parallelization of a seeded region growing segmentation of brain images for a GPU clusterAnna M. Westhoff. 1-8 [doi]
• A Quantitative Comparison of PRAM based Emulated Shared Memory Architectures to Current Multicore CPUs and GPUsErik Hansson, Erik Alnervik, Christoph Kessler, Martti Forsell. 1-7 [doi]
• Temporal Separation for Hardware-Based I/O Virtualization for Mixed-Criticality Embedded Real-Time Systems Using PCIe SR-IOVDaniel Münch, Michael Paulitsch, Andreas Herkersdorf. 1-7 [doi]
• Simultaneous Self-Configuration with Multiple Managers for Organic Computing SystemsNizar Msadek, Rolf Kiefhaber, Theo Ungerer. 1-7 [doi]
• Engineering and Mastering Interwoven SystemsSven Tomforde, Joerg Haehner, Hella Seebach, Wolfgang Reif, Bernhard Sick, Arno Wacker, Ingo Scholtes. 1-8 [doi]
• A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAMGo Matsukawa, Yohei Nakata, Yuta Kimi, Yasuo Sugure, Masafumi Shimozawa, Shigeru Oho, Hiroshi Kawaguchi, Masahiko Yoshimoto, Masahiko Yoshimoto. 1-5 [doi]
• ScaFES: An Open-Source Framework for Explicit Solvers Combining High-Scalability with User-FriendlinessMartin Flehmig, Kim Feldhoff, Ulf Markwardt. 1-8 [doi]
• Improving Efficiency of Embedded Multi-core Platforms with Scratchpad MemoriesJohny Paul, Walter Stechele, Manfred Kröhnert, Tamim Asfour. 1-8 [doi]
• An Architecture Framework for Porting Applications to FPGAsFabian Nowak, Michael Bromberger, Wolfgang Karl. 1-7 [doi]
• An Approach to Enhance Loop Performance for Multicluster VLIW DSP ProcessorYangzhao Yang, Naijie Gu, Kaixin Ren, Bingqing Hu. 1-8 [doi]
• Towards Tight Interaction of ASP and SMT Solving for System-Level Decision MakingAlexander Biewer, Jens Gladigau, Christian Haubelt. 1-7 [doi]
• Experimental Generation of Configurable Circuits for Rotationally Symmetric FunctionsAndreas C. Doering. 1-5 [doi]
• A comparison of CUDA and OpenACC: Accelerating the Tsunami Simulation EasyWaveSteffen Christgau, Johannes Spazier, Bettina Schnor, Martin Hammitzsch, Andrey Babeyko, Joachim Waechter. 1-5 [doi]
• Unstructured Membership Management for Byzantine Fault Tolerance in CloudsJongBeom Lim, Daeyong Jung, Taeweon Suh, Heon-Chang Yu. 1-8 [doi]
• FALP: A Fault Adaptive and Low Power Method for Network on Chip RouterFarhad Mohammadian. 1-7 [doi]
• Performance Engineering for a Medical Imaging Application on the Intel Xeon Phi AcceleratorJohannes Hofmann, Jan Treibig, Georg Hager, Gerhard Wellein. 1-8 [doi]
• Robust Scheduling in a Self-Organizing Hierarchy of Autonomous Virtual Power PlantsGerrit Anders, Alexander Schiendorfer, Jan-Philipp Steghöfer, Wolfgang Reif. 1-8 [doi]
• Towards a Reliability-aware Design Flow for Kahn Process Networks on NoC-based MultiprocessorsOnur Derin, Leandro Fiorin. 1-8 [doi]
• PBA2CUDA - A Framework for Parallelizing Population Based Algorithms Using CUDAIoannis Zgeras, Jürgen Brehm, Michael Knoppik. 1-6 [doi]
• Multi-Objective Diagnosis of Non-Permanent Faults in Many-Core SystemsPeter Waszecki, Martin Lukasiewycz, Samarjit Chakraborty. 1-8 [doi]
• Towards Actor-oriented Programming on PGAS-based Multicore ArchitecturesSascha Roloff, Frank Hannig, Jürgen Teich. 1-2 [doi]
• Reflection Processes Help Integrate Simultaneous Self-Optimization ProcessesKirstie L. Bellman, Christopher Landauer. 1-5 [doi]
• Evaluation of Adaptive Memory Management Techniques on the Tilera TILE-Gx PlatformTobias Fleig, Oliver Mattes, Wolfgang Karl. 1-8 [doi]
• Evaluating the Energy Efficiency of Reconfigurable Computing Toward Heterogeneous Multi-Core ComputingFabian Nowak. 1-6 [doi]
• The Invasive Network on Chip - A Multi-Objective Many-Core Communication InfrastructureJan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Martin Karle, Maximilian Singh, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker. 1-8 [doi]
• A Perfomance Study of Parallel Cauchy Reed/Solomon CodingPeter Sobe, Peter Schumann. 1-6 [doi]