Abstract is missing.
- Trade-Off Between Performance, Fault Tolerance and Energy Consumption in Duplication-Based Taskgraph SchedulingPatrick Eitschberger, Simon Holmbacka, Jörg Keller 0001. 3-17 [doi]
- Lipsi: Probably the Smallest Processor in the WorldMartin Schoeberl. 18-30 [doi]
- Superlinear Scalability in Parallel Computing and Multi-robot Systems: Shared Resources, Collaboration, and Network TopologyHeiko Hamann. 31-42 [doi]
- Closed Loop Controller for Multicore Real-Time SystemsJohannes Freitag, Sascha Uhrig. 45-56 [doi]
- Optimization of the GNU OpenMP Synchronization Barrier in MPSoCMaxime France-Pillois, Jérôme Martin, Frédéric Rousseau. 57-69 [doi]
- Ampehre: An Open Source Measurement Framework for Heterogeneous Compute NodesAchim Lösch, Alex Wiens, Marco Platzner. 73-84 [doi]
- A Hybrid Approach for Runtime Analysis Using a Cycle and Instruction Accurate ModelSebastian Rachuj, Christian Herglotz, Marc Reichenbach, André Kaup, Dietmar Fey. 85-96 [doi]
- A CAM-Free Exascalable HPC Router for Low-Energy CommunicationsCaroline Concatto, Jose Antonio Pascual, Javier Navaridas, Joshua Lant, Andrew Attwood, Mikel Luján, John Goodacre. 99-111 [doi]
- Lightweight Hardware Synchronization for Avoiding Buffer Overflows in Network-on-ChipsMartin Frieb, Alexander Stegmeier, Jörg Mische, Theo Ungerer. 112-126 [doi]
- Network Optimization for Safety-Critical Systems Using Software-Defined NetworksCora Perner. 127-138 [doi]
- CaCAO: Complex and Compositional Atomic Operations for NoC-Based Manycore PlatformsSven Rheindt, Andreas Schenk, Akshay Srivatsa, Thomas Wild, Andreas Herkersdorf. 139-152 [doi]
- Redundant Execution on Heterogeneous Multi-cores Utilizing Transactional MemoryRico Amslinger, Sebastian Weis, Christian Piatka, Florian Haas, Theo Ungerer. 155-167 [doi]
- Improving the Performance of STT-MRAM LLC Through Enhanced Cache Replacement PolicyPierre-Yves Péneau, David Novo, Florent Bruguier, Lionel Torres, Gilles Sassatelli, Abdoulaye Gamatié. 168-180 [doi]
- On Automated Feedback-Driven Data Placement in Multi-tiered MemoryT. Chad Effler, Adam P. Howard, Tong Zhou, Michael R. Jantz, Kshitij A. Doshi, Prasad A. Kulkarni. 181-194 [doi]
- Operational Characterization of Weak Memory Consistency ModelsM. Senftleben, K. Schneider. 195-208 [doi]
- A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power ModeYasumasa Chidai, Kojiro Izuoka, Ryota Shioya, Masahiro Goshima, Hideki Ando. 211-224 [doi]
- Performance-Energy Trade-off in CMPs with Per-Core DVFSSolomon Abera, M. Balakrishnan, Anshul Kumar. 225-238 [doi]
- Towards Fine-Grained DVFS in Embedded Multi-core CPUsGiuseppe Massari, Federico Terraneo, Michele Zanella, Davide Zoni. 239-251 [doi]
- Evaluating Auto-adaptation Methods for Fine-Grained Adaptable ProcessorsJoost Hoozemans, Jeroen van Straten, Zaid Al-Ars, Stephan Wong. 255-268 [doi]
- HLS Enabled Partially Reconfigurable Module ImplementationNicolae Bogdan Grigore, Charalampos Kritikakis, Dirk Koch. 269-282 [doi]
- Hardware Acceleration in Genode OS Using Dynamic Partial ReconfigurationAlexander Dörflinger, Mark Albers, Björn Fiethe, Harald Michalik. 283-293 [doi]
- Do Iterative Solvers Benefit from Approximate Computing? An Evaluation Study Considering Orthogonal Approximation MethodsMichael Bromberger, Markus Hoffmann, Robin Rehrmann. 297-310 [doi]
- A Flexible FPGA-Based Inference Architecture for Pruned Deep Neural NetworksThorbjörn Posewsky, Daniel Ziener. 311-323 [doi]