Abstract is missing.
- High-Performance Front-End Embedded Signal Processors for Adaptive Sensor ArraysWilliam S. Song. [doi]
- Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD ArchitecturesRuby B. Lee. 3-14 [doi]
- Architecture of an Image Rendering Co-Processor for MPEG-4 SystemsMladen Berekovic, Peter Pirsch, Thorsten Selinger, Kai-Immo Wels, Carolina Miro, Anne Lafage, Christoph Heer, Giovanni Ghigo. 15-24 [doi]
- A Multiplication-Free Parallel Architecture for Affine TransformationWael M. Badawy, Magdy A. Bayoumi. 25-34 [doi]
- A Simple RISC Microprocessor Core Designed for Digital Set-Top-Box ApplicationsMarco Antonio Dal Poz, J. Aedo Cobo, Wilhelmus A. M. Van Noije, Marcelo Knörich Zuffo. 35 [doi]
- Formal Verification for Microprocessors with Extendable Instruction SetSergej Sawitzki, Rainer G. Spallek, Jens Schönherr, Bernd Straube. 47-55 [doi]
- Compiling Image Processing Applications to Reconfigurable HardwareRobert Rinker, Jeffrey Hammes, Walid A. Najjar, A. P. Wim Böhm, Bruce A. Draper. 56-65 [doi]
- Integration of High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia FunctionalityHolger Blume, Hans-Martin Blüthgen, Christiane Henning, Patrick Osterloh. 66 [doi]
- High Level Modeling for Parallel Executions of Nested Loop AlgorithmsEd F. Deprettere, Edwin Rijpkema, Paul Lieverse, Bart Kienhuis. 79-91 [doi]
- Minimal Complexity Hierarchical Loop Representations of SFG Processors for Optimal High Level SynthesisAndrew Stone, Elias S. Manolakos. 92-102 [doi]
- High Level Synthesis for Peak Power Minimization Using ILPWen-Tsong Shiue. 103-112 [doi]
- High-Level Synthesis of Nonprogrammable Hardware AcceleratorsRobert Schreiber, Shail Aditya, B. Ramakrishna Rau, Vinod Kathail, Scott A. Mahlke, Santosh G. Abraham, Greg Snider. 113 [doi]
- Implementing 1, 024-Bit RSA Exponentiation on a 32-Bit Processor CoreB. J. Phillips, N. Burgess. 127-137 [doi]
- Bit Permutation Instructions for Accelerating Software CryptographyZhijie Shi, Ruby B. Lee. 138-148 [doi]
- Performance-Scalable Array Architectures for Modular MultiplicationWilliam L. Freking, Keshab K. Parhi. 149 [doi]
- A 108 Gbps, 1.5 GHz 1D-DCT ArchitectureAhmed M. Shams, Magdy A. Bayoumi. 163-172 [doi]
- Efficient VLSI Architectures for Baseband Signal Processing in Wireless Base-Station ReceiversSridhar Rajagopal, Srikrishna Bhashyam, Joseph R. Cavallaro, Behnaam Aazhang. 173-184 [doi]
- A Vector Multiprocessor for Real-Time Multi-User Detection in Spread-Spectrum CommunicationNaraig Manjikian. 185-194 [doi]
- A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-mu m CMOS Viterbi DecoderV. S. Gierenz, Oliver Weiss, Tobias G. Noll, I. Carew, J. Ashley, R. Karabed. 195 [doi]
- A Booth Multiplier Accepting Both a Redundant or a Non-Redundant Input with No Additional DelayMarc Daumas, David W. Matula. 205-214 [doi]
- A Hardware Algorithm for Variable-Precision LogarithmJavier Hormigo, Julio Villalba, Michael J. Schulte. 215-224 [doi]
- Block-Update Parallel Processing QRD-RLS Algorithm for Throughput Improvement with Low Power ConsumptionLijun Gao, Keshab K. Parhi. 225-234 [doi]
- A 16-Bit x 16-Bit MAC Design Using Fast 5: 2 CompressorsOhsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka. 235 [doi]
- Control for High-Speed PE ArraysMartin C. Herbordt, Honghai Zhang, Calvin Lin, Hong Rao, Jade Cravy. 247-257 [doi]
- Explicit SIMD Programming for Asynchronous ApplicationsAndrea Di Blas, Richard Hughey. 258-267 [doi]
- Quadratic Control Signals in Linear Systolic ArraysScott Bowden, Doran Wilde, Sanjay V. Rajopadhye. 268-275 [doi]
- Contention-Conscious Transaction Ordering in Embedded MultiprocessorsMukul Khandelia, Shuvra S. Bhattacharyya. 276 [doi]
- Architecture for Wavelet Packet Transform with Best Tree SearchingMaría A. Trenas, Juan López, Manuel Sánchez, Emilio L. Zapata, Francisco Argüello. 289-298 [doi]
- Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software SorterMarcus Bednara, Oliver Beyer, Jürgen Teich, Rolf Wanka. 299-308 [doi]
- A Programmable Processor for Approximate String Matching with High Throughput RateHans-Martin Blüthgen, Tobias G. Noll. 309 [doi]
- A New Algorithm for the Elimination of Common Subexpressions in Hardware Implementation of Digital Filters by Using Genetic ProgrammingH. Safiri, Majid Ahmadi, Graham A. Jullien, William C. Miller. 319-328 [doi]
- A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded ProcessorsRamaswamy Govindarajan, Erik R. Altman, Guang R. Gao. 329-338 [doi]
- Partitioning Conditional Data Flow Graphs for Embedded System DesignMichel Auguin, Luc Bianco, L. Capella, Emmanuel Gresset. 339-348 [doi]
- Generation of Scheduling Functions Supporting LSGP-PartitioningDirk Fimmel. 349 [doi]