Table of Contents

• Program Committee [doi]
• Message from the Conference Chairs [doi]
• External Referees [doi]
• Configurable Computing Platforms - Promises, PromisesCarl Ebeling. 3-4 [doi]
• The Mythical CCM: In Search of Usable (and Resuable) FPGA-Based General Computing MachinesBrent E. Nelson. 5-14 [doi]
• Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on ChipBo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, Ingrid Verbauwhede. 15-18 [doi]
• The Molen FemtoJava EngineJúlio C. B. de Mattos, Stephan Wong, Luigi Carro. 19-22 [doi]
• A Generic Multi-Phase On-Chip Traffic Generation EnvironmentAntoine Scherrer, Antoine Fraboulet, Tanguy Risset. 23-27 [doi]
• Minimum Cost for Channels and Registers in Processor Arrays by Avoiding RedundancySebastian Siegel, Renate Merker. 28-32 [doi]
• NoC Hot Spot minimization Using AntNet Dynamic Routing AlgorithmMasoud Daneshtalab, Ashkan Sobhani, Ali Afzali-Kusha, Omid Fatemi, Zainalabedin Navabi. 33-38 [doi]
• Recent Developments in Configurable and Extensible ProcessorsGrant Martin. 39-44 [doi]
• Software Configurable ProcessorsJeffrey M. Arnold. 45-49 [doi]
• Reconfigurable Hardware and Software Architectural Constructs for the Enablement of Resilient Computing SystemsPaul L. Master. 50-55 [doi]
• Application Specific Processing: A Tools ApproachDrew Taussig, Andreas Hoffmann, Achim Nohl, Andrea Kroll. 56-64 [doi]
• Fast Bit Compression and Expansion with Parallel Extract and Parallel Deposit InstructionsYedidya Hilewitz, Ruby B. Lee. 65-72 [doi]
• A Mesh-of-Trees Interconnection Network for Single-Chip Parallel ProcessingAydin O. Balkan, Gang Qu, Uzi Vishkin. 73-80 [doi]
• Reconfigurable Shuffle Network Design in LDPC DecodersJun Tang, Tejas Bhatt, Vishwas Sundaramurthy. 81-86 [doi]
• 2D-VLIW: An Architecture Based on the Geometry of ComputationRicardo Santos, Rodolfo Azevedo, Guido Araujo. 87-94 [doi]
• An Efficient Implementation of High-Accuracy Finite Difference Computing Engine on FPGAsChuan He, Guan Qin, Mi Lu, Wei Zhao. 95-98 [doi]
• Performance Evaluation of a Novel Direct Table Lookup Method and Architecture with Application to 16-bit Integer FunctionsLun Li, Alex Fit-Florea, Mitchell A. Thornton, David W. Matula. 99-104 [doi]
• Design of Radix-4 SRT Dividers in 65 Nanometer CMOS TechnologyTung N. Pham, Earl E. Swartzlander Jr.. 105-108 [doi]
• Describing Quantum Circuits with Systolic ArraysAasavari Bhave, Eurípides Montagne, Edgar Granados. 109-113 [doi]
• FPGA Implementation of Beamforming Receivers Based on MRC and NC-LMS for DS-CDMA SystemElie H. Sarraf, Messaoud Ahmed-Ouameur, Daniel Massicotte. 114-117 [doi]
• Low Complexity Design of High Speed Parallel Decision Feedback EqualizersDaesun Oh, Keshab K. Parhi. 118-124 [doi]
• Quantitative Analysis of Embedded FPGA-Architectures for ArithmeticThorsten von Sydow, B. Neumann, Holger Blume, Tobias G. Noll. 125-131 [doi]
• A Cost Effective Pipelined Divider for Double Precision Floating Point NumberSandeep B. Singh, Jayanta Biswas, S. K. Nandy. 132-137 [doi]
• A 64-bit Decimal Floating-Point ComparatorIvan D. Castellanos, James E. Stine. 138-144 [doi]
• Pipelined Range Reduction for Floating Point NumbersFrancisco J. Jaime, Julio Villalba, Javier Hormigo, Emilio L. Zapata. 145-152 [doi]
• Systolic FFT Processors: Past, Present and FutureEarl E. Swartzlander Jr.. 153-158 [doi]
• From Bit Level Systolic Arrays to HDTV Processor ChipsJohn V. McCanny, Roger F. Woods, John G. McWhirter. 159-162 [doi]
• The UCSC Kestrel Application-Unspecific ProcessorRichard Hughey, Andrea Di Blas. 163-168 [doi]
• Multicore processors as Array Processors: Research OpportunitiesPeter R. Cappello. 169-172 [doi]
• Analysis of a Fully-Scalable Digital Fractional Clock DividerThomas B. Preuber, Rainer G. Spallek. 173-177 [doi]
• Voltage Assignment and Loop Scheduling for Energy Minimization while Satisfying Timing Constraint with Guaranteed ProbabilityMei Kang Qiu, Chun Xue, Qingfeng Zhuge, Zili Shao, Meilin Liu, Edwin Hsing-Mean Sha. 178-181 [doi]
• Parallel Processing Based Power Reduction in a 256 State Viterbi DecoderWoo Hyung Lee, Pinaki Mazumder. 182-185 [doi]
• Affine Nested Loop Programs and their Binary Parameterized Dataflow Graph CounterpartsEd F. Deprettere, Todor Stefanov, Shuvra S. Bhattacharyya, Mainak Sen. 186-190 [doi]
• Polyhedral Modeling and Analysis of Memory Access ProfilesPhilippe Clauss, Bénédicte Kenmei. 191-198 [doi]
• Array Processing Using Alternate Arithmetic - A 20 Year LegacyGraham A. Jullien. 199-204 [doi]
• Loop Transformation Methodologies for Array-Oriented Memory ManagementFlorin Balasa, Per Gunnar Kjeldsberg, Martin Palkovic, Arnout Vandecappelle, Francky Catthoor. 205-212 [doi]
• An Overview of Systolic Array Concepts and Applications for Linear Algebra and Signal ProcessingKung Yao, Flavio Lorenzelli. 213 [doi]
• Three Computationally Demanding Problems in Search of ASAP SolutionsDaniel P. Lopresti. 214-222 [doi]
• Parameterized Looped Schedules for Compact Representationof Execution SequencesMing-Yung Ko, Claudiu Zissulescu, Sebastian Puthenpurayil. 223-230 [doi]
• An Improved Systolic Architecture for LU DecompositionDaeGon Kim, Sanjay V. Rajopadhye. 231-238 [doi]
• Dual-Processor Design of Energy Efficient Fault-Tolerant SystemShaoxiong Hua, Pushkin R. Pari, Gang Qu. 239-244 [doi]
• An Energy-Delay Efficient Subword Permutation UnitGiorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos. 245-252 [doi]
• Architecture design of an H.264/AVC decoder for real-time FPGA implementationThomas Warsaw, Marcin Lukowiak. 253-256 [doi]
• Dynamic Voltage Scaling for Power Efficient MPEG4-SP ImplementationAntoni Portero, Guillermo Talavera, Marius Monton, Borja Martínez, Francky Catthoor, Jordi Carrabina. 257-260 [doi]
• Dynamic-SIMD for lens distortion compensationBart Mesman, Hamed Fatemi, Henk Corporaal, Twan Basten. 261-264 [doi]
• High Speed Channel Coding Architectures for the Uncoordinated OR ChannelHerwin Chan, Miguel Griot, Andres I. Vila Casado, Richard D. Wesel, Ingrid Verbauwhede. 265-268 [doi]
• Efficient Group KeyManagement with Tamper-resistant ISA ExtensionsYoutao Zhang, Jun Yang, Lan Gao. 269-274 [doi]
• Speeding Up AES By Extending a 32 bit Processor Instruction SetGuido Bertoni, Luca Breveglieri, Farina Roberto, Francesco Regazzoni. 275-282 [doi]
• Buffer and register allocation for memory space optimizationYoucef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Fabien Coelho. 283-290 [doi]
• New Schemes in Clustered VLIW Processors Applied to Turbo DecodingPablo Ituero, Marisa López-Vallejo. 291-296 [doi]
• Evaluating Hardware Support for Reference Counting Using Software Configurable ProcessorsFeng Xian, Witawas Srisa-an, Hong Jiang. 297-302 [doi]
• Architectural Support on Object-Oriented Programming in a JAVA ProcessorYiyu Tan, Chihang Yau, Anthony S. Fong. 303-310 [doi]
• Reconfigurable Fixed Point Dense and Sparse Matrix-Vector Multiply/Add UnitHumberto Calderon, Stamatis Vassiliadis. 311-316 [doi]
• High Performance VLSI Architecture Design for H.264 CAVLC DecoderMythri Alle, Jayanta Biswas, S. K. Nandy. 317-322 [doi]
• An FPGA-Based Application-Specific Processor for Efficient Reduction of Multiple Variable-Length Floating-Point Data SetsGerald R. Morris, Viktor K. Prasanna, Richard D. Anderson. 323-330 [doi]
• A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image ProcessingHritam Dutta, Frank Hannig, Jürgen Teich, Benno Heigl, Heinz Hornegger. 331-340 [doi]
• An Adaptable And Scalable Asymmetric Cryptographic ProcessorNeil Smyth, Máire McLoone, John V. McCanny. 341-346 [doi]
• Low-Cost Elliptic Curve Digital Signature Coprocessor for Smart CardsGuerric Meurice de Dormale, Renaud Ambroise, David Bol, Jean-Jacques Quisquater, Jean-Didier Legat. 347-353 [doi]
• Throughput Optimized SHA-1 Architecture Using Unfolding TransformationYong Ki Lee, Herwin Chan, Ingrid Verbauwhede. 354-359 [doi]
• Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and ImplementationMarjan Karkooti, Predrag Radosavljevic, Joseph R. Cavallaro. 360-367 [doi]