Abstract is missing.
- High-speed GaAs MESFET Digital IC Design for Optical Communication SystemsKimikazu Sano, Koichi Narahara, Koichi Murata, Taiichi Otsuji, Kiyomitsu Onodera. 1-5
- Design and Experimental Results of a 2V-Operation Single-Chip GaAs T/R-MMIC Front-End for 1.9-GHz Personal CommunicationsKazuya Yamamoto, Takao Moriwaki, Yutaka Yoshii, Takayuki Fujii, Jun Otsuji, Yoshinobu Sasaki, Yukio Miyazaki, Kazuo Nishitani. 7-12
- HW-SW Co-Synthesis: The Present and The Future (Embedded Tutorial)Sri Parameswaran. 19-22
- Parallelization in Co-Compilation for Configurable AcceleratorsJürgen Becker, Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger. 23-33
- Delay and Noise Formulas for Capacitively Coupled Distributed RC LinesHiroshi Kawaguchi, Takayasu Sakurai. 35-43
- Reduced Order Macromodel of Coupled Interconnects for Timing and Functional Verification of Sub Half-micron IC DesignsDavide Pandini, Primo Scandolara, Carlo Guardiani. 45-50
- A New LSI Performance Prediction Model for Interconnection Analysis of Future LSIsShuji Takahashi, Masato Edahiro, Yoshihiro Hayashi. 51-56
- New Methods to Find Optimal Non-Disjoint Bi-DecompositionsShigeru Yamashita, Hiroshi Sawada, Akira Nagoya. 59-68
- A Heuristic Algorithm to Design AND-OR-EXOR Three-Level NetworksDebatosh Debnath, Tsutomu Sasao. 69-74
- ETDD-Based Synthesis of Term-Based FPGAs for Incompletely Specified Boolean FunctionsGueesang Lee, Rolf Drechsler. 75-80
- Function Decomposition and Synthesis Using Linear SiftingChristoph Meinel, Fabio Somenzi, Thorsten Theobald. 81-86
- Optimized Array Index Computation in DSP ProgramsRainer Leupers, Anupam Basu, Peter Marwedel. 87-92
- Binding and Scheduling Algorithms for Highly Retargetable CompilationMasayuki Yamaguchi, Nagisa Ishiura, Takashi Kambe. 93-98
- Unrolling Loops With Indeterminate Loop Counts in System Level PipelinesHui Guo, Sri Parameswaran. 99-104
- Quantitative Selection of Media BenchmarksChunho Lee, Miodrag Potkonjak. 105-110
- Reliable Threshold Voltage Determination for Sub-0.1µm Gate Length MOSFET sMorikazu Tsuno, Masato Suga, Masayasu Tanaka, Kentaro Shibahara, Michiko Miura-Mattausch, Masataka Hirose. 111-116
- Inverse Modeling - A Promising Approach to Know What Is Made and What Should Be MadeSeiichiro Yamaguchi, Hiroshi Goto. 117-121
- TCAD/DA for MPU and ASIC DevelopmentHiroo Masuda, Katsumi Tsuneno, Hisako Sato, Kazutaka Mori. 129-134
- Logical-Physical Co-design for Deep Submicron Circuits: Challenges and Solutions (Embedded Tutorial)Massoud Pedram. 137-142
- A Low Power 2-D DCT Chip Design Using Direct 2-D AlgorithmLiang-Gee Chen, Juing-Ying Jiu, Hao-Chieh Chang, Yung-Pin Lee, Chung-Wei Ku. 145-150
- Low Power Realization of FIR Filters Implemented using Distributed ArithmeticMahesh Mehendale, Amit Sinha, Sunil D. Sherlekar. 151-156
- An Efficient Variable-Length Tap FIR Filter ChipSung Hyun Yoon, Myung Hoon Sunwoo. 157-161
- Effective Simulation for the Giga-scale Massively Parallel Supercomputer SR2201Kaoru Suzuki, Shunsuke Miyamoto, Masato Kurosaki, Junji Nakagoshi. 163-168
- A Top-down Hardware/Software Co-Simulation Method for Embedded Systems Based Upon a Component Logical Bus ArchitectureMitsuhiro Yasuda, Katsuhiko Seo, Hisao Koizumi, Barry Shackleford, Fumio Suzuki. 169-175
- A Hardware Software Cosimulation Backplane with Automatic Interface GenerationWonyong Sung, Soonhoi Ha. 177-182
- On the CSC Property of Signal Transition Graph Specifications for Asynchronous Circuit DesignMohit Sahni, Takashi Nanya. 183-189
- Practical Synthesis of Speed-Independent Circuits Using UnfoldingsUisok Kim, Dong-Ik Lee. 191-196
- Automated Design of Wave Pipelined Multiport Register FilesKouji Takano, Takehito Sasaki, Nobuyuki Oba, Hiroaki Kobayashi, Tadao Nakamura. 197-202
- Considering Testability during High-level Design (Embedded Tutorial)Sujit Dey, Anand Raghunathan, Rabindra K. Roy. 205-210
- Partial Scan Design Methods Based on Internally Balanced StructureTomoya Takasaki, Tomoo Inoue, Hideo Fujiwara. 211-216
- Model Checking: Its Basics and Reality (Embedded Tutorial)Masahiro Fujita. 217-222
- A Survey for Pass-Transistor Logic Technologies - Recent Researches and Developments and Future Prospects (Embedded Tutorial)Kazuo Taki. 223-226
- ALPS: An Automatic Layouter for Pass-Transistor Cell SynthesisYasuhiko Sasaki, Kunihito Rikino, Kazuo Yano. 227-232
- Hierarchy - A CHDStd Tool for the Coming Deep Submicron Complex Design CrisisS. Grout, G. Ledenbach, R. G. Bushroe, P. Fisher, D. Cottrell, D. Mallis, S. DasGupta, J. Morrell, J. Sayah, R. Gupta, P. T. Patel, P. Adams. 257-260
- ATM Cell Modelling using Objective VHDLAlberto Allara, Massimo Bombana, Patrizia Cavalloro, Wolfgang Nebel, Wolfram Putzke-Röming, Martin Radetzki. 261-264
- A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow GraphsNozomu Togawa, Takafumi Hisaki, Masao Yanagisawa, Tatsuo Ohtsuki. 265-274
- Module Selection Using Manufacturing InformationHiroyuki Tomiyama, Hiroto Yasuura. 275-281
- Techniques for Functional Test Pattern ExecutionInki Hong, Miodrag Potkonjak. 283-288
- Heterogeneous BISR-approach using System Level Synthesis FlexibilityInki Hong, Miodrag Potkonjak, Ramesh Karri. 289-294
- An Integrated Flow for Technology Remapping and Placement of Sub-half-micron CircuitsJinan Lou, Amir H. Salek, Massoud Pedram. 295-300
- Scan-chain Optimization Algorithms for Multiple Scan-pathsSusumu Kobayashi, Masato Edahiro, Mikio Kubo. 301-306
- Power Reduction in Microprocessor Chips by Gated Clock RoutingJaewon Oh, Massoud Pedram. 313-318
- TITAC-2: An Asynchronous 32-bit MicroprocessorAkihiro Takamura, Motokazu Ozawa, Izumi Fukasaku, Taro Fujii, Yoichiro Ueno, Masashi Imai, Masashi Kuwako, Takashi Nanya. 319-320
- Low Power Micoprocessors for Comparative Study on Bus Architecture and Multiplexer ArchitectureSatoshi Komatsu, Makoto Ikeda, Kunihiro Asada. 323-324
- Metacore: A Configurable and Instruction Level Extensible DSP CoreJin-Hyuk Yang, Byung-Woon Kim, Sung-Won Seo, Sang-Jun Nam, Chang-Ho Ryu, Jang Ho Cho, Chong-Min Kyung. 325-326
- FPGA for High-Performance Bit-Serial Pipeline DatapathTsuyoshi Isshiki, Takenobu Shimizugashira, Akihisa Ohta, Imanuddin Amril, Hiroaki Kunieda. 331-332
- A Low Power 50MHz FFT Processor with Cyclic Extension and Shaping FilterM. Bickerstaff, T. Arivoli, Philip J. Ryan, Neil Weste, David J. Skellern. 335-336
- The MINC (Multistage Interconnection Network with Cache Control Mechanism) ChipTakashi Midorikawa, Takayuki Kamei, Toshihiro Hanawa, Hideharu Amano. 337-338
- A CMOS Smart Image Sensor LSI for Focal-Plane CompressionShoji Kawahito, Makoto Yoshida, Masaaki Sasaki, Daisuke Miyazaki, Yoshiaki Tadokoro, Kenji Murata, Shiro Doushou, Akira Matsuzawa. 339-340
- A ±1.5V 4MHz Low-Pass Gm-C Filter in CMOSChangsik Yoo, Wonchan Kim. 341-342
- Motion Adaptive Image SensorTakayuki Hamamoto, Kiyoharu Aizawa, Mitsutoshi Hatori. 343-344
- Timing Analysis and Optimization: From Devices to Systems (Abstract of Embedded Tutorial)Anirudh Devgan, Sandip Kundu. 345
- Dual-loop Digital PLL Design for Adaptive Clock RecoveryTae Hun Kim, Beomsup Kim. 347-352
- High-Level Estimation Techniques for Usage in Hardware/Software Co-DesignJörg Henkel, Rolf Ernst. 353-360
- Loop Pipelining in Hardware-Software PartitioningJinhwan Jeon, Kiyoung Choi. 361-366
- A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM SizesNguyen-Ngoc Bình, Masaharu Imai, Yoshinori Takeuchi. 367-372
- Simultaneous Wire Sizing and Wire Spacing in Post-Layout Performance OptimizationJiang-An He, Hideaki Kobayashi. 373-378
- Curvilinear Detailed Routing Algorithm and Its Extension to Wire-Spreading and Wire-FatteningToshiyuki Hama, Hiroaki Etoh. 385-390
- An Analysis on VLSI Interconnection Considering Skin EffectTetsuhisa Mido, Kunihiro Asada. 403-408
- Design of Nonlinear Switched-Current Circuits Using Building Block ApproachX. Zeng, P. S. Tang, C. K. Tse. 409-414
- A New Design for Double Edge Triggered Flip-flopsMassoud Pedram, Qing Wu, Xunwei Wu. 417-421
- Space- and Time-Efficient BDD Construction via Working Set ControlBwolen Yang, Yirng-An Chen, Randal E. Bryant, David R. O Hallaron. 423-432
- Manipulation of *BMDsRolf Drechsler, Stefan Höreth. 433-438
- Reconfigurable Systems: A Survey (Embedded Tutorial)Toshiaki Miyazaki. 447-452
- Reconfigurable Systems: Activities in Asia and South Pacific (Embedded Tutorial)Hideharu Amano, Yuichiro Shibata. 453-457
- Interchangeable Boolean Functions and Their Effects on Redundancy in Logic CircuitsDebesh K. Das, Susanta Chakraborty, Bhargab B. Bhattacharya. 469-474
- Real Time Fault Injection Using Logic EmulatorsReza Sedaghat-Maman, Erich Barke. 475-479
- A Fast and Accurate Method of Redesigning Analog Subcircuits for Technology ScalingSeiji Funaba, Akihiro Kitagawa, Toshiro Tsukada, Goichi Yokomizo. 489-494
- A Novel Design Assistant for Analog CircuitsMarkus Wolf, Ulrich Kleine, Frédéric Schafer. 495-500
- Automatic Test Generation for Linear Analog Circuits under Parameter VariationsC.-J. Richard Shi, Michael W. Tian. 501-506
- The Ensparsed LU Decomposition Method for Large Scale Circuit Transient AnalysisReiji Suda, Yoshio Oyanagi. 507-512
- FPART: A Multi-way FPGA Partitioning Procedure Based on the Improved FM AlgorithmRongzheng Zhou, Jiarong Tong, PuShan Tang. 513-518
- An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate ArraysNozomu Togawa, Kayoko Hagi, Masao Yanagisawa, Tatsuo Ohtsuki. 519-526
- An Architecture-oriented Routing Method for FPGAs Having Rich Hierarchical Routing ResourcesTakahiro Murooka, Atsushi Takahara, Toshiaki Miyazaki, Akihiro Tsutsui. 527-533
- On the Optimal Sub-routing Structures of 2-D FPGA Greedy Routing ArchitecturesJiaofeng Pan, Yu-Liang Wu, C. K. Wong. 535-540
- Mixed-Signal Hardware Description Languages in the Era of System-on-Silicon: Challenges and Opportunities (Abstract of Embedded Tutorial)C.-J. Richard Shi. 543
- Power Reduction in PipelinesSri Parameswaran, Hui Guo. 545-550
- A Hybrid Power Model for RTL Power EstimationYi-Min Jiang, Shi-Yu Huang, Kwang-Ting Cheng, Deborah C. Wang, ChingYen Ho. 551-556
- Synthesis of Power Efficient Systems-on-SiliconDarko Kirovski, Chunho Lee, Miodrag Potkonjak, William H. Mangione-Smith. 557-562
- Air-Pressure-Model-Based Fast Algorithms for General FloorplanTomonori Izumi, Atsushi Takahashi, Yoji Kajitani. 563-570
- Module Placement on BSG-Structure with Pre-Placed Modules and Rectilinear ModulesShigetoshi Nakatake, Masahiro Furuya, Yoji Kajitani. 571-576
- A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block LayoutTetsushi Koide, Shin ichi Wakabayashi. 577-583
- VLSI for Multimedia U-NII WLANsNeil Weste, David J. Skellern, Terry Percival. 585-587
- Low-Power Implementation of H.324 Audiovisual Codec Dedicated to Mobile ComputingTakao Onoye, Gen Fujita, Hiroyuki Okuhata, Morgan Hirosuke Miki, Isao Shirakawa. 589-594
- CMOS Image Sensors with Video CompressionShoji Kawahito, Yoshiaki Tadokoro, Akira Matsuzawa. 595-600