Abstract is missing.
- A Variable Instruction Stream Extension to the VLIW ArchitectureAndrew Wolfe, John Paul Shen. 2-14
- Reducing the Branch Penalty by Rearranging Instructions in Double-Width MemoryManolis Katevenis, Nestoras Tzartzanis. 15-27
- Software PrefetchingDavid Callahan, Ken Kennedy, Allan Porterfield. 40-52
- High-Bandwidth Data Memory Systems for Superscalar ProcessorsGurindar S. Sohi, Manoj Franklin. 53-62
- The Cache Performance and Optimizations of Blocked AlgorithmsMonica S. Lam, Edward E. Rothberg, Michael E. Wolf. 63-74
- The Effect of Context Switches on Cache PerformanceJeffrey C. Mogul, Anita Borg. 75-84
- A Portable Interface for On-the-Fly Instruction Space ModifictionDavid Keppel. 86-95
- Virtual Memory Primitives for User ProgramsAndrew W. Appel, Kai Li. 96-107
- The Interaction of Architecture and Operating System DesignThomas E. Anderson, Henry M. Levy, Brian N. Bershad, Edward D. Lazowska. 108-120
- Integrating Register Allocation and Instruction Scheduling for RISCsDavid G. Bradlee, Susan J. Eggers, Robert R. Henry. 122-131
- Code Generation for Streaming: An Access/Execute MechanismManuel E. Benitez, Jack W. Davidson. 132-141
- Efficient Implementation of High Level Parallel ProgramsRajive Bagrodia, Sharad Mathur. 142-151
- Vector Register Design for Polycyclic Vector SchedulingWilliam H. Mangione-Smith, Santosh G. Abraham, Edward S. Davidson. 154-163
- Fine-Grain Parallelism with Minimal Hardware Support: A Compiler-Controlled Threaded Abstract MachineDavid E. Culler, Anurag Sah, Klaus E. Schauser, Thorsten von Eicken, John Wawrzynek. 164-175
- Limits of Instruction-Level ParallelismDavid W. Wall. 176-188
- Performance Consequences of Parity Placement in Disk ArraysEdward K. Lee, Randy H. Katz. 190-199
- Integration of Compression and Caching for a Two-Level File SystemVincent Cate, Thomas R. Gross. 200-211
- NUMA Policies and Their Relation to Memory ArchitectureWilliam J. Bolosky, Michael L. Scott, Robert P. Fitzgerald, Robert J. Fowler, Alan L. Cox. 212-221
- LimitLESS Directories: A Scalable Cache Coherence SchemeDavid Chaiken, John Kubiatowicz, Anant Agarwal. 224-234
- An Efficient Cache-Based Access Anomaly Detection SchemeSang Lyul Min, Jong-Deok Choi. 235-244
- Performance Evaluation of Memory Consistency Models for Shared Memory MultiprocessorsKourosh Gharachorloo, Anoop Gupta, John L. Hennessy. 245-257
- Process Coordination with Fetch-and-IncrementEric Freudenthal, Allan Gottlieb. 260-268
- Synchronization without ContentionJohn M. Mellor-Crummey, Michael L. Scott. 269-278
- The Case for a Read BarrierDouglas Johnson. 279-287
- An Analysis of SPARC and MIPS Instruction Set Utilization on the SPEC BenchmarksRobert F. Cmelik, Shing I. Kong, David R. Ditzel, Edmund J. Kelly. 290-302
- Performance Characteristics of Architectural Features of the IBM RISC System/6000C. Brian Hall, Kevin O Brien. 303-309
- Performance From Architecture: Comparing a RISC and CISC with Similar Hardware OrganizationDileep Bhandarkar, Douglas W. Clark. 310-319